1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a refresh control circuit of a semiconductor apparatus.
2. Related Art
As illustrated in FIG. 1, a refresh control circuit 1 of a semiconductor apparatus according to the conventional art includes a piled delay unit 10, a delay unit 20, first to fourth variable delay units 30, 40, 50, and 60, and a precharge control unit 70.
The piled delay unit 10 generates a plurality of row active signals RACT<0:7> in response to a refresh signal REF and a refresh mode signal RMODE.
The plurality of row active signals RACT<0:7> may then be activated at a predetermined time interval according to the refresh mode signal RMODE.
The delay unit 20 delays the plurality of row active signals RACT<0:7> by a predetermined time and generates a plurality of row address strobe signals IRAS<0:7>.
The delay unit 20 includes a plurality of delays 21 to 28.
The plurality of variable delay units 30, 40, 50, and 60 delay the plurality of row address strobe signals IRAS<0:7> by a delay time determined by the refresh mode signal RMODE, and generate a plurality of refresh period pulse signals RE<0:3>.
The variable delay unit 30 delays a signal, which is obtained by logically operating (for example, ORing) the row address strobe signals IRAS<0, 7> by the delay time determined by the refresh mode signal RMODE, and generates a refresh period pulse signal RE<0>.
The variable delay unit 40 delays a signal, which is obtained by logically operating (for example, ORing) the row address strobe signals IRAS<3, 4> by the delay time determined by the refresh mode signal RMODE, and generates a refresh period pulse signal RE<1>.
The variable delay unit 50 delays a signal, which is obtained by logically operating (for example, ORing) the row address strobe signals IRAS<2, 5> by the delay time determined by the refresh mode signal RMODE, and generates a refresh period pulse signal RE<2>.
The variable delay unit 60 delays a signal, which is obtained by logically operating (for example, ORing) the row address strobe signals IRAS<1, 6> by the delay time determined by the refresh mode signal RMODE, and generates a refresh period pulse signal RE<3>.
The precharge control unit 70 controls the piled delay unit 10 in response to the plurality of refresh period pulse signals RE<0:3>, and deactivates the plurality of row active signals RACT<0:7>.
FIG. 1 illustrates an example in which the semiconductor apparatus includes first to eight memory banks BK0 to BK7 (not shown), and supports a 4 piled operation. Memory banks with the same order are refreshed for a period in which the plurality of row active signals RACT<0:7> are activated.
The 4 piled operation then indicates a refresh scheme in which four row active signal groups RACT<0, 7>, RACT<3, 4>, RACT<2, 5>, and RACT<1, 6> are activated at a predetermined time interval.
The conventional art includes a plurality of variable delay units, such as variable delay units 30, 40, 50, and 60, such that the 4 piled operation is supported.
However, the four variable delay units 30, 40, 50, and 60 attribute to an increase in circuit area of the refresh control circuit, resulting in a reduction of a layout margin of the semiconductor apparatus. Accordingly, when supporting a piled operation beyond the 4 piled operation such as an 8 piled operation, eight variable delay units are required, resulting in a significant increase in circuit area.